As chips become more complicated with larger amounts of gates, cores, and memories being integrated into them, efficient test methods become more important. At the same time, as technology nodes become smaller, defects (particularly AC defects) can become more difficult to detect. This drives more focus on test quality, which in turn can increase complexity for test circuitry and often test circuit area. Any method that allows for the easy minimization of test time and test circuit area becomes beneficial.
Parallel array BIST test methods typically allow for the highest quality memory test. However, parallel array BIST test methods often require more chip area to implement than other array BIST test methods. A large amount of the overhead associated with parallel array BIST test methods are the comparison circuits used to compare all output values from a memory under test with all expected values and generate pass/fail information along with information on the failing bit location. This comparison and test data generation circuitry often takes the form of complex logic trees that can become quite large. These complex logic trees are often contained in a block of logic local to each memory under test, typically referred to as a BIO macro, or BIST Input/Output macro. The area of these comparison trees could be amortized across numerous memories (the BIO logic could be shared). However, these memories would then need to be tested sequentially (memory A tested using the comparison tree, then memory B tested using the comparison tree, then memory C for example). Typical off-the shelf array BIST circuits would normally be configured to simply test the largest possible total memory size (memory A size+memory B size+memory C size). However, in cases where the comparison tree was only shared amongst memory A and memory B, the BIST testing would typically continue operating as if memory C were still in place, needlessly extending the test time.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove in a manner that does not require complicated software control or customized circuit designs.